Verilog: Frequently Asked Questions : Language, Applications and Extensions
Contents: Foreword. Preface. Acknowledgments. I. Basic Verilog: 1. Assignments. 2. Tasks and functions. 3. Parameters. 4. Ports. II. RTL Design: 1. Assignments. 2. Tasks and functions. 3. Storage elements. 4. Flow-control constructs. 5. Finite state machines. 6. Memories. 7. General design considerations. 8. Multiple clock design considerations. 9. Common "Gotchas" in synthesizable RTL. 10. Coding techniques for area minimization. 11. Coding for better static timing optimization. 12. Design for testability (DFT) considerations. 13. Power reduction considerations. III. Verification: 1. Messaging. 2. Behavioral functional models (BFMs). 3. Bus monitors. 4. Random stimulus generation. 5. Stimulus generation. 6. Gate level simulations. IV. Miscellaneous. V. Common mistakes: 1. Some common errors that are not detected at compile-time. VI. Verilog during simulation regressions. References. Index.
"Verilog: Frequently Asked Questions: Language, Applications and Extensions addresses "front end" questions and issues encountered in using-the Verilog HDL, during all the stages of Hardware Design, Synthesis and verification. The issues discussed in the book are typically encountered in both ASIC design projects as well as in Soft IP designs. These issues are addressed in a simple Q&A format. Since each issue is independently dealt with and explained in detail, this book acts as an important source of reference for the Verilog users. Each of the FAQs will be illustrated with figures and tables as required. The latest Verilog-2001 and system Verilog have also been referred to in this book.
With the increasing complexity of ASICs being designed these days, the decisions that one makes in any of the stages of design, synthesis or verification has profound effects on these three stages. Verilog: Frequently Asked Questions: Language, Applications and Extensions presents the intricacies of these inter-dependent issues in the context of the Verilog HDL."
